Struct dma

• Defined in File dma.h

Struct Documentation

struct dma

DMA with separate read and write masters

Public Functions

inline uint16_t get_INTR() volatile

Get INTR’s INTR field.

Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

inline void set_INTR(uint16_t value) volatile

Set INTR’s INTR field.

Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

inline uint16_t get_TIMER0_Y() volatile

Get TIMER0’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER0_Y(uint16_t value) volatile

Set TIMER0’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER0_X() volatile

Get TIMER0’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER0_X(uint16_t value) volatile

Set TIMER0’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER0(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER0’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER0(uint16_t Y, uint16_t X) volatile

Set all of TIMER0’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER1_Y() volatile

Get TIMER1’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER1_Y(uint16_t value) volatile

Set TIMER1’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER1_X() volatile

Get TIMER1’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER1_X(uint16_t value) volatile

Set TIMER1’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER1(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER1’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER1(uint16_t Y, uint16_t X) volatile

Set all of TIMER1’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER2_Y() volatile

Get TIMER2’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER2_Y(uint16_t value) volatile

Set TIMER2’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER2_X() volatile

Get TIMER2’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER2_X(uint16_t value) volatile

Set TIMER2’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER2(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER2’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER2(uint16_t Y, uint16_t X) volatile

Set all of TIMER2’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_TIMER3_Y() volatile

Get TIMER3’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline void set_TIMER3_Y(uint16_t value) volatile

Set TIMER3’s Y field.

Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.

inline uint16_t get_TIMER3_X() volatile

Get TIMER3’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void set_TIMER3_X(uint16_t value) volatile

Set TIMER3’s X field.

Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.

inline void get_TIMER3(uint16_t &Y, uint16_t &X) volatile

Get all of TIMER3’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline void set_TIMER3(uint16_t Y, uint16_t X) volatile

Set all of TIMER3’s bit fields.

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

inline uint16_t get_MULTI_CHAN_TRIGGER() volatile

Get MULTI_CHAN_TRIGGER’s MULTI_CHAN_TRIGGER field.

Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel’s trigger register; the channel will start if it is currently enabled and not already busy.

inline void set_MULTI_CHAN_TRIGGER(uint16_t value) volatile

Set MULTI_CHAN_TRIGGER’s MULTI_CHAN_TRIGGER field.

Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel’s trigger register; the channel will start if it is currently enabled and not already busy.

inline bool get_SNIFF_CTRL_EN() volatile

Get SNIFF_CTRL’s EN bit.

Enable sniffer

inline void set_SNIFF_CTRL_EN() volatile

Set SNIFF_CTRL’s EN bit.

Enable sniffer

inline void clear_SNIFF_CTRL_EN() volatile

Clear SNIFF_CTRL’s EN bit.

Enable sniffer

inline void toggle_SNIFF_CTRL_EN() volatile

Toggle SNIFF_CTRL’s EN bit.

Enable sniffer

inline uint8_t get_SNIFF_CTRL_DMACH() volatile

Get SNIFF_CTRL’s DMACH field.

DMA channel for Sniffer to observe

inline void set_SNIFF_CTRL_DMACH(uint8_t value) volatile

Set SNIFF_CTRL’s DMACH field.

DMA channel for Sniffer to observe

inline DMA_SNIFF_CTRL_CALC get_SNIFF_CTRL_CALC() volatile

Get SNIFF_CTRL’s CALC field.

inline void set_SNIFF_CTRL_CALC(DMA_SNIFF_CTRL_CALC value) volatile

Set SNIFF_CTRL’s CALC field.

inline bool get_SNIFF_CTRL_BSWAP() volatile

Get SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void set_SNIFF_CTRL_BSWAP() volatile

Set SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void clear_SNIFF_CTRL_BSWAP() volatile

Clear SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline void toggle_SNIFF_CTRL_BSWAP() volatile

Toggle SNIFF_CTRL’s BSWAP bit.

Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer’s point of view.

inline bool get_SNIFF_CTRL_OUT_REV() volatile

Get SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void set_SNIFF_CTRL_OUT_REV() volatile

Set SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void clear_SNIFF_CTRL_OUT_REV() volatile

Clear SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void toggle_SNIFF_CTRL_OUT_REV() volatile

Toggle SNIFF_CTRL’s OUT_REV bit.

If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline bool get_SNIFF_CTRL_OUT_INV() volatile

Get SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void set_SNIFF_CTRL_OUT_INV() volatile

Set SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void clear_SNIFF_CTRL_OUT_INV() volatile

Clear SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void toggle_SNIFF_CTRL_OUT_INV() volatile

Toggle SNIFF_CTRL’s OUT_INV bit.

If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.

inline void get_SNIFF_CTRL(bool &EN, uint8_t &DMACH, DMA_SNIFF_CTRL_CALC &CALC, bool &BSWAP, bool &OUT_REV, bool &OUT_INV) volatile

Get all of SNIFF_CTRL’s bit fields.

(read-write) Sniffer Control

inline void set_SNIFF_CTRL(bool EN, uint8_t DMACH, DMA_SNIFF_CTRL_CALC CALC, bool BSWAP, bool OUT_REV, bool OUT_INV) volatile

Set all of SNIFF_CTRL’s bit fields.

(read-write) Sniffer Control

inline uint8_t get_FIFO_LEVELS_TDF_LVL() volatile

Get FIFO_LEVELS’s TDF_LVL field.

Current Transfer-Data-FIFO fill level

inline uint8_t get_FIFO_LEVELS_WAF_LVL() volatile

Get FIFO_LEVELS’s WAF_LVL field.

Current Write-Address-FIFO fill level

inline uint8_t get_FIFO_LEVELS_RAF_LVL() volatile

Get FIFO_LEVELS’s RAF_LVL field.

Current Read-Address-FIFO fill level

inline void get_FIFO_LEVELS(uint8_t &TDF_LVL, uint8_t &WAF_LVL, uint8_t &RAF_LVL) volatile

Get all of FIFO_LEVELS’s bit fields.

(read-only) Debug RAF, WAF, TDF levels

inline uint16_t get_CHAN_ABORT() volatile

Get CHAN_ABORT’s CHAN_ABORT field.

Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.

inline void set_CHAN_ABORT(uint16_t value) volatile

Set CHAN_ABORT’s CHAN_ABORT field.

Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.

inline uint8_t get_N_CHANNELS() volatile

Get N_CHANNELS’s N_CHANNELS field.

Public Members

dma_control CONTROL[CONTROL_length]

uint32_t INTR

(read-write) Interrupt Status (raw)

interrupt_cluster INT0

const uint32_t reserved_padding0 = {}

interrupt_cluster INT1

uint32_t TIMER0

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER1

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER2

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t TIMER3

(read-write) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

uint32_t MULTI_CHAN_TRIGGER

(read-write) Trigger one or more channels simultaneously

uint32_t SNIFF_CTRL

(read-write) Sniffer Control

uint32_t SNIFF_DATA

(read-write) Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

const uint32_t reserved_padding1 = {}

const uint32_t FIFO_LEVELS = {}

(read-only) Debug RAF, WAF, TDF levels

uint32_t CHAN_ABORT

(read-write) Abort an in-progress transfer sequence on one or more channels

const uint32_t N_CHANNELS = {}

(read-only) The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

const uint32_t reserved_padding2[reserved_padding2_length] = {}

dma_debug DEBUG[DEBUG_length]

Public Static Attributes

static constexpr struct_id_t id = 7

dma’s identifier.

static constexpr std::size_t size = 3072

dma’s size in bytes.

static constexpr std::size_t CONTROL_length = 16

static constexpr std::size_t reserved_padding2_length = 237

static constexpr std::size_t DEBUG_length = 16